For 14 nanometer (nm) and beyond devices, a combination of replacement metal gate (RMG) and FinFET processes are typically utilized. However, as the pitch continues to scale down beyond 14 nm devices, the edge formed during a gate cut, which is cut earlier in the process to form or separate the gates, becomes closer to the adjacent fin. This cut is typically done during the poly gate patterning. As a result, a barrier layer and metal fill lie between the inter-layer dielectric (ILD). This creates a physical stress near the adjacent fin and requires a metal fill at the gate cut boundary between the fins and an inter-layer dielectric. These factors can cause overall device performance degradation
Therefore, it may be desirable to develop methods of fabricating devices with no barrier layer or metal fill near the fins of the device.